So far we've designed quite a few chips, but now let's finish out the last two basic ones - NOR and XNOR
┌───────────┐
IN[0] ●─┤ │
│ NOR ├─● OUT
IN[1] ●─┤ │
└───────────┘
┌────────────┐
IN[0] ●─┤ │
│ XNOR ├─● OUT
IN[1] ●─┤ │
└────────────┘
Each chip has 2 IN pins and 1 OUT pin.
The NOR chip only transmits power with neither IN pin is powered.
The XNOR chip only transmits power when both IN pins are the same state.
NOR.IN ║ NOR.OUT
────────║─────────
00 ║ 1
01 ║ 0
10 ║ 0
11 ║ 0
XNOR.IN ║ XNOR.OUT
─────────║──────────
00 ║ 1
01 ║ 0
10 ║ 0
11 ║ 1
The circuit board will come pre-installed with INPUT and OUTPUT chips as shown below:
───────┐
├─● OUT[0]
│
├─● OUT[1] ┌────────
│ IN[0] ●─┤
INPUT │ │ OUTPUT
│ IN[1] ●─┤
├─● OUT[2] └────────
│
├─● OUT[3]
───────┘
This problem will combine the development of both the NOR and XNOR chips,
so you must simulate placing both chips in the following configuration:
───────┐ ┌───────────┐
├─● ----------- ●─┤ │
│ │ NOR ├─● ------┐
├─● ----------- ●─┤ │ : ┌────────
│ └───────────┘ └----- ●─┤
INPUT │ │ OUTPUT
│ ┌────────────┐ ┌----- ●─┤
├─● ----------- ●─┤ │ : └────────
│ │ XNOR ├─● -----┘
├─● ----------- ●─┤ │
───────┘ └────────────┘
Digital Logic Circuit Interface
For these Digital Logic Circuits tasks, you will not be providing an answer string you would for other tasks.
Instead, your Solution Code will be interpreted directly to place chips onto the circuitboard and connect them with wires.
Click here to learn the Digital Logic Circuit Syntax used on this site.
After the chips have been placed and connected, the server will run a series of tests, randomly assigning values to the input pin(s) and checking to see if the output pins read the corresponding expected values. If all tests produce the expected outputs, then the circuitboard is considered a success.
Even though we won't be using the "Your answer" box, you'll still need to put something in that box to submit your solution. Just put anything - it will not be passed to the interpreter.
Truth Table
Design a circuit board which satisfies the following Truth Table:
INPUT.OUT ║ OUTPUT.IN
───────────║───────────
0000 ║ 11
0001 ║ 10
0010 ║ 10
0011 ║ 11
0100 ║ 01
0101 ║ 00
0110 ║ 00
0111 ║ 01
1000 ║ 01
1001 ║ 00
1010 ║ 00
1011 ║ 01
1100 ║ 01
1101 ║ 00
1110 ║ 00
1111 ║ 01